1. Field of the Invention
The present invention relates to a memory interface circuit which has prefetch buffers for improving the fetch efficiency of instruction data that is fetched from a memory by a central processor such as a microprocessor.
2. Description of the Related Art
For improving the fetch efficiency of instruction data, a cache memory is typically interposed between a microprocessor and a main memory. Recently, various techniques have been proposed for the sake of a further improvement in the fetch efficiency of the cache memory.
For example, there has been proposed a technique in which a plurality of pieces of instruction data corresponding to the top address and subsequent addresses of an interruption are transferred to the cache memory during a period between when the microprocessor receives an interruption request and when it starts the interruption processing, thereby yielding a cache hit at the time of the interruption processing (disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2000-347931).
Besides, there has been proposed a technique in which a cache memory dedicated to interruption is provided aside from a normal cache memory in order to improve the cache hit efficiency after a return from interruption processing (disclosed in, for example, Japanese Unexamined Patent Application Publication No. Hei 6-28258).
Moreover, there has been proposed a technique pertaining to an interruption request circuit of a microprocessor, in which top addresses corresponding to interruption request sources are stored into a memory previously in order to reduce the time for searching for the interruption request sources (disclosed in, for example, Japanese Unexamined Patent Application Publication No. Sho 62-259158).
Meanwhile, there has been proposed a memory interface circuit which is provided with a prefetch buffer of small memory capacity instead of the cache memory, allowing a cost reduction without a drop in instruction fetch efficiency. In this technology, the prefetch buffer stores branch addresses alone. The memory interface circuit prefetches instruction data at an address obtained by incrementing the previous address by one when the address output from the microprocessor is not a branch address. Thus, instruction data corresponding to consecutive addresses can be read in a short access time equivalent to cache hits. Besides, if the instruction data corresponding to a branch address lies in the prefetch buffer, it can be read in a short access time equivalent to a cache hit.